This proposal outlines the development and validation of Mitsubishi Electric's SiC MOSFET modules that utilize the body diode for industrial applications. Traditional SiC modules rely on Schottky Barrier Diodes (SBDs) in anti-parallel with MOSFETs. By leveraging the inherent body diode, the new design reduces parasitic capacitance, frees up chip space, and simplifies circuit design. However, the body diode is susceptible to bipolar degradation caused by stacking faults from basal plane dislocations (BPDs).
To mitigate bipolar degradation, Mitsubishi Electric developed a 2nd generation planar SiC MOSFET with a high concentration of electrons in the buffer layer. This buffer layer prevents holes from reaching the substrate, thereby suppressing stacking fault expansion and ensuring long-term reliability.
To validate reliability, over 477,000 chips were subjected to bipolar stress. Statistical analysis revealed that only a few chips exhibited a V_DS(on) shift greater than 10%, confirming the effectiveness of the buffer layer. The degradation probability at the chip level was then converted to module-level estimates using statistical models. The estimated probability of a V_DS(on) shift over 5% is less than 100 ppm, meeting industrial quality standards.
To confirm that chips with V_DS(on) would not be problematic in long term operation, chip with shifts from 6% to 89% were subjected to HTRB, HTGB, repetitive switching, and dynamic avalanche tests. All samples passed, showing no significant degradation. Gate reliability was assessed using AC-BTI tests, where Mitsubishi’s MOSFETs demonstrated superior gate threshold voltage (V_GS(th)) stability compared to competitors.
