Soitec’s SmartSiC™ engineered substrate enables significant switching and conduction improvements for 1200 V SiC MOSFETs by addressing the temperature-dependent limitations of the body diode’s reverse recovery charge (Qrr). Traditional recombination center methods lower Qrr but at the cost of increasing the body diode’s forward voltage drop (Vf), thereby degrading third-quadrant conduction. SmartSiC™ breaks this trade-off by using an ultra low resistivity poly-SiC handle wafer ( < 5 mΩ·cm), resulting in a 13% RDSon reduction and a 29% drop in reverse recovery energy (Err) at high temperature and current. Notably, these benefits are achieved without compromising diode Vf, under third-quadrant conduction. This will lead to a 30% reduction in Eon drift with temperature, contributing to better switching stability. Overall, both conduction and switching losses are reduced in first and third quadrants, enhancing PFC stage full-load efficiency. These gains support Titanium or Ruby grade power supply designs with reduced thermal stress and compact packaging. SmartSiC™ thus enables high-frequency, high-density applications with fewer thermal constraints.
