D26.4 - Formulating Critical Performance Limits and Power Stage Design in Multiphase Voltage Regulators with Input Voltage and Power FET Technology Scaling

With the increasing computational demands of the data center applications, multi-phase buck converters remain an attractive power management solution for the second stage of the two-stage 48V bus architecture. Compared to the conventional 12V intermediate bus architecture, a 4-6V bus provides an efficient two-stage VRM solution. This reduced intermediate bus voltage enables vertical power delivery and reduces the PDN losses. It also enables the use of DrMOS and trench MOSFET, along with high-frequency operation, resulting in a highly compact and efficient solution for the second stage. However, it is crucial to evaluate the impact of reduced bus voltage on the response of the second stage. This digest serves as a design tool and presents an analytical approach to evaluate how the reduced intermediate bus voltage affects the time-optimal transient response, passives, and efficiency compared to the conventional 12V bus architecture. Simulation results demonstrate the improved efficiency and transient performance for the 4.8V bus over the 12V bus. A two-phase buck converter hardware prototype is fabricated operating at 1MHz, and a few experimental results are presented.