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Hardware-in-the-Loop, Digital Twins and Rapid Prototyping

T35.1 - Development of Oscillation Canceller for DC Resonance Induced by CPL Using Power Hardware-in-the-Loop Simulation

Thursday, March 26, 2026
10:20 AM - 10:40 AM CT
Location: 214C
In a DC microgrid, the increasing presence of Constant Power Loads (CPL) may lead to instability in the DC voltage due to the CPL’s negative resistance characteristic. This paper presents an active voltage oscillation suppression method that utilizes an Oscillation Canceller (OC) for stabilization. The target system consists of four parallel CPLs powered by an AC/DC converter. A sequential verification framework—consisting of impedance-based stability analysis, Model-in-the-Loop (MIL) offline simulation, and Power Hardware-in-the-Loop (PHIL) simulation testing—is employed. Theoretical predictions are validated through MIL simulations, and the effectiveness of the OC is demonstrated. To address the challenge of accurately emulating CPL behavior in PHIL environments, a novel variant of the Damping Impedance Method (DIM), termed Admittance-based Partial Virtual DIM, is introduced. Experimental results confirm the feasibility and effectiveness of the proposed methodology.