Skip to main content
APEC 2026 Main banner

Power Factor Correction

T38.2 - Design and Implementation of Three-Phase Six-Switch Power Factor Corrector with DC-Link Capacitor Voltage Balance

Thursday, March 26, 2026
10:40 AM - 11:00 AM CT
Location: 217B
High power factor correction (PFC) topologies are important nowadays. The three-phase six-switch power factor corrector offers fewer components and simple control method but suffers from dc bus capacitors voltage imbalance. To balance the voltages of dc bus capacitors, voltage error signal between the series connected dc bus capacitors is adopted to modulate the dc offset of the sinusoidal modulation signal. An experimental prototype of three-phase six-switch power factor corrector is implemented with ac voltage of 220 Vrms / 60 Hz, dc voltage of 800 V, switching frequency of 50 kHz, and rated power of 10 kW. The experimental results show a maximum efficiency is 98.5% at output power of 8 kW. With the dc-link capacitor voltage balance, the bus voltage imbalance problem is mitigated, and the total current harmonic distortion (THDi) is within 4.7% with power factor of 0.991.