The increasing functional density and operating frequencies of modern electronic systems have intensified the challenges of multilayer printed circuit board (PCB) design. High-speed, high-density layouts must meet signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) requirements. Conventional maze-search autorouting algorithms, such as Lee’s and A*, optimize path length and computation but often fail to address multi-objective constraints such as via minimization and conflict resolution in three-dimensional routing. This paper presents an enhanced multilayer PCB autorouting method that extends A* with an eight-direction Chebyshev distance heuristic, a composite cost function for both path length and via penalties, and dynamic re-routing for conflict resolution. Evaluated on a two-layer DC–DC converter PCB, the proposed algorithm achieved 100% routing completion, reduced average path length by 21.55%, via count by 50.00%, and search time by 55.71% compared with conventional A*. These results demonstrate its effectiveness for dense, constraint-driven layouts and its potential for SI- and EMC-aware routing in high-performance designs.
