T03.1 - 48V Power Delivery for AI Computing Systems: IVR-Oriented Architecture and Topology Selection

Tuesday, March 24, 2026

8:30 AM - 8:50 AM CT

Location: 214C

Technical Lecture Presenter(s)

Jingyi Yuan

University of Science and Technology of China

Presentation

Co-Author(s)

WS

Wen Sun

University of Science and Technology of China
ZW

Zikang Wang

University of Science and Technology of China
Yichao Ji

University of Science and Technology of China
Zeguo Liu, PhD (he/him/his)

University of Science and Technology of China
MS

Minghao Shang

University of Science and Technology of China
QM

Qingqing Min

University of Science and Technology of China
LC

Lin Cheng

University of Science and Technology of China

48 V vertical power delivery combined with integrated voltage regulator (IVR) has proven highly effective in reducing I2R losses. Moreover, high power density of IVR enables placement close to the end load, simplifying power delivery networks (PDNs). Together with their fast transient response, the supply-voltage guard band can be reduced, achieving significant system-level power savings. This work reviews advances in single-stage and multi-stage architectures and topologies, and proposes an IVR-oriented framework for architecture and topology selection. Specifically, IVRs based on low-voltage (LV) BCD or GaN technologies achieve high-voltage, high-power delivery at 5-10 MHz, typically paired with transformer-based fixed-ratio topologies for high efficiency and low cost. In contrast, advanced-CMOS-stacked IVRs support ultrafast transient responses at tens to hundreds of MHz, but require intermediate-bus-voltage (IBV) regulation to protect LV devices from overvoltage stress during transients. To address this, hybrid switched-capacitor with multi-inductor topologies are adopted to enhance both power density and reliability.