Current power delivery network technology has reached its limit, restricting performance even though the processors and accelerator engines that power these data centers are fabricated using the most advanced microarchitectures and manufacturing process nodes. Faced with rising core counts, reduced operating voltages, higher current flows and adoption of chiplet-based architectures, power delivery network designers are being dually challenged by increased power density and reduced availability of passive-component real estate. The Saras Tile, or STILE™, offers a new paradigm for in-package power delivery that significantly improves efficiency and performance while freeing up package real estate to enable higher levels of chiplet integration. A multi-domain, substrate-embedded, passive module, STILE™ is designed to support the growing number of power rails within the package. STILE™ enables the move of power regulation from system board to package. STILE™ is designed to significantly improve the performance and efficiency of power delivery networks.
