Technische Universität Dortmund
T22.9 - Active Gate Driver with Controllable Drain-to-Gate Capacitive Coupling for Voltage Overshoot Reduction in SiC MOSFETs
Wednesday, March 25, 20264:40 PM - 5:00 PM CT
D22.4 - Accurate MHz-Range Hysteresis Simulation via a Delay-Enhanced Jiles-Atherton Model in Verilog-A
Thursday, March 26, 202612:00 PM - 1:45 PM CT
