High-resolution digital pulse-width modulation (HRDPWM) is vital for fast-switching power electronics. This work introduces a hybrid method combining Serializer/Deserializer (SERDES) primitives operated in Double Data Rate (DDR) mode with deterministic clock-phase-switching. The approach achieves sub-nanosecond resolution without asynchronous delay elements while keeping counter logic at lower frequencies. By design, the architecture is robust to process-voltage-temperature (PVT) variations and has been validated on AMD/Xilinx Artix-7 and Ultrascale+ devices. A 1 MHz synchronous buck converter, as part of a 48 V–1 V sigma converter, demonstrates its effectiveness. Experimental results show a minimum timing resolution of 227 ps, excellent duty cycle linearity (R² > 0.99996), and low jitter. While not achieving absolute state-of-the-art in every metric, the method provides a balanced, high-class performance across all categories with straightforward implementation, meeting the practical demands of modern converter topologies.
.jpg "Roberto Petrella (he/him/his) photo")