Low frequency, or quasistatic, capacitance measurements for semiconductor devices, including high power devices, is important. Traps are typically characterized by comparison of both low and high frequency C-V methods. Knowledge of trap behavior is critical for device performance. Measuring instruments typically force a voltage and measure current and time to derive the capacitance. However, SiC power devices have much higher capacitance than their silicon counterparts which makes the low frequency C-V measurements much more challenging. Using ammeters to measure current on higher capacitance devices typically causes noisy results. To overcome unstable readings, the new method forces a DC current and measures the voltage and time. The capacitance is derived from the measured current, voltage, and time using a differential technique. This differential technique enables more stable and accurate capacitance extraction, offering engineers a more reliable method for evaluating trap behavior in high-capacitance devices like SiC. This paper discusses a 3-step technique for measuring quasistatic C-V using a single SMU on SiC MOSFETs and MOScaps, the differences between low and high frequency C-V results, comparisons of results from different manufacturers, and a proposed method to derive the interface trap density.
