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WBG Integration and Reliability

D04.5 - Optimization Framework for Hard-Switching Transients of Power Semiconductor Devices to Minimize Switching Losses and EMC-Relevant Noise Emissions

Thursday, March 26, 2026
12:00 PM - 1:45 PM CT
Location: Hemisfair Ballroom
This paper presents an optimization framework for hard-switching transients of power semiconductor devices that simultaneously minimizes switching losses and electromagnetic emissions (EME) while respecting component constraints. The framework integrates a state-space simulation environment with lab-verified SiC MOSFET models, a genetic algorithmbased optimizer providing quasi-continuous gate current control through variable resistance arrays, and a novel cost function incorporating the Heisenberg-Gabor inequality for broadband EME quantification. Unlike existing approaches focusing on sequential parameter adjustment or single-frequency ringing reduction, this framework enables systematic analysis of loss-EME trade-offs with high temporal resolution. The framework reveals that optimized gate current profiles exhibit bell-shaped pulses achieving sigmoidal voltage transitions, establishing a foundation for future work, including gate loop design and power semiconductor device optimization.