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WBG Integration and Reliability

D04.4 - Gate-Delay Optimization Strategy for Balancing Dynamic ON-Resistance and Power Loss in GaN/Si Hybrid Switches

Thursday, March 26, 2026
12:00 PM - 1:45 PM CT
Location: Hemisfair Ballroom
The single die size gallium nitride (GaN) devices are still limited by the relatively immature process technology and cost. Thus, paralleling GaN devices are necessary for high-power applications. However, there are remarkable difficulties in paralleling GaN devices considering the extremely fast switching speed and dynamic on-resistance (dRDS,on) degradation. As a result, the hybrid switch (HyS) with GaN/Si parallel connection becomes an optimized solution, which improves the system-level long-term reliability by sharing the switching stress for GaN devices. In this work, the GaN/Si HyS is proposed with a gate-driving delay modulation to optimize the d$R_{DS,on}$. The optimal delay is determined by a novel optimization strategy considering the dRDS,on and loss. Via 400-V double pulse test (DPT) experiments, the dRDS,on is reduced by 8.2-12.2%, and the turn-on loss is reduced by 5.3-17.2%, compared to the conventional modulation across a current range of 10 A to 25 A. It demonstrates that the strategic gate-driving delay time for the GaN/Si HyS makes an optimal balance between loss and reliability.