This paper presents a design-space exploration (DSE) study of a 22-kW non-isolated integrated onboard charger (iOBC) that combines a three-level neutral-point-clamped (3L-NPC) AC--DC stage with a midpoint-referenced interleaved dual-buck DC--DC stage, implemented using 650-V GaN devices. A parametric sweep is performed over DC-link voltage (700~V and 800~V), output voltage (300~V, 400~V, and 500~V), AC--DC switching frequency (12--24~kHz), and DC--DC switching frequency (300--900~kHz). Two complementary design scenarios are introduced: M1 resizes passives to maintain constant ripple targets to quantify passive reduction enabled by frequency, while M2 fixes passives to isolate frequency-driven loss and thermal trends. The 3L-NPC limits device stress to approximately \(\Vdc/2\), enabling 650-V GaN operation at \(\Vdc \approx 800\)~V. The back-end Interleaved Dual-Buck inherently produces low CMV by cancellation of switch-node steps.
