Skip to main content
APEC 2026 Main banner

    GaN and SiC Devices and Modules

    D25.5 - Switching Loss Characterization with Uncertainty Quantification for 3.3 kV Monolithic Versus Discrete SiC Bidirectional FETs

    Thursday, March 26, 2026
    12:00 PM - 1:45 PM CT
    Location: Poster 3
    This work presents a systematic investigation into the switching losses of 3.3 kV SiC bidirectional field-effect transistors (BiDFETs) in common-drain configuration. Hard-switching characterization is performed at 2 kV bus voltage, 5–20 A load currents, and 30–150°C case temperatures. The first quantitative comparison between monolithic and discrete (two-chip) architectures reveals that monolithic integration exhibits higher switching losses due to tighter capacitive coupling. Gate drive configuration impact is also quantified: turn-on energy exhibits negligible sensitivity to single- versus dual-gate driving, while turn-off energy shows measurable reduction under dual-gate operation due to reduced body diode reverse recovery. These findings are enabled by a power-based integration framework with uncertainty quantification, which maintains measurement confidence in the presence of post-switching oscillations extending beyond standard IEC 60747-8 windows. The results provide foundational switching characteristics and architecture selection guidelines for medium-voltage SiC BiDFET implementation in circuits.