T30.5 - Closed-Loop Slew Rate Control of Active Current Source Gate Driver with Analog IC Design for SiC MOSFET

Thursday, March 26, 2026

9:40 AM - 10:00 AM CT

Location: 217B

Technical Lecture Presenter(s)

Wen Xin Wu, PhD (she/her/hers)

National Taiwan University

Presentation

Co-Author(s)

WL

Wei-Ru Lin

National Taiwan University
WK

Wen Lin Ko

National Taiwan University
GW

Guan-You Wu

National Taiwan University
CC

Ching Jan Chen

Department of Electrical Engineering, National Taiwan University
Giao Huu Thuc (he/him/his)

Department of Electrical Engineering, National Taiwan University/ Leadtrend Technology Corporation

This paper proposes an Active Current Source Gate Driver (ACSD) designed for SiC MOSFETs packaged in a TO-247-4L configuration. The proposed driver controls the drain current Ids slew rate during turn-on and the drain-source voltage Vds slew rate during turn-off. In the proposed ACSD, the output stage of the gate driver employs a current source with a partial continuous current path, which shortens bias establishment time, enhances switching response speed and enables more precise regulation of the output current. In the control section, the maximum slew rate is detected using an analog approach. This peak value is captured by a sample-and-hold circuit and fed back into the system, achieving accurate control of the peak slew rate. Finally, a Boost Converter is utilized as a multi-pulse test circuit to verify the controllability and performance of the proposed gate driver.