SiC power devices, operating in high-power, high-temperature environments, are subjected to severe thermomechanical stress, resulting in significant reliability challenges. Device condition monitoring (CM) provides valuable proactive measures to improve circuit reliability and prevent catastrophic failures. Classic CM approaches require routine maintenance shutdowns and frequent operation interruptions and demand large space, cost and power. In this work, an in-driver on-chip CM technique is proposed, which constructs the device CM circuitry as part of gate driver design, and carries out its operation autonomously without interrupting system operation at very low power and silicon overheads. To enhance accuracy and reliability of the on-chip CM, a 2-D multi-level TON delay sensing scheme is employed, which measures both the aging condition and aging stage with high noise immunity. To validate the approach, an integrated circuit (IC) prototype has been fabricated using the TSMC 180nm BCD process, achieving a power consumption of 2.78mW and occupying an active die area of 0.0817mm², which leads to 3.63% and 4.84% silicon and power overheads respectively to the entire gate driver IC.
