The series resonant balancing converter (SRBC) can be adopted for efficient active control of the DC bus capacitor voltage unbalance of power converters, allowing a reduction of the needed capacitor volume and associated costs. High reduction of volume can be achieved by increasing the switching frequency of the SRBC, which dictates for soft switching to limit the efficiency drop. At high operating frequency and the desired small value of resonant inductance, zero-voltage switching (ZVS) of the SRBC is strongly affected by circuit losses and associated distortion of the resonant current waveform, leading to the possibility of loss of ZVS in half of the switching transitions. This condition needs to be considered in the design of the resonant tank. Novel analytical models considering losses and the interlock delay time are proposed in this paper allowing to analyze the limits of ZVS in the high frequency operation and to propose converter design guidelines for ensuring reliable soft-switching operation. Experimental results taken from a 3 kW hardware prototype, which achieves a peak efficiency of 99.5 % at a switching frequency of 1.3 MHz, verify the accuracy of the proposed models.